FPGA Implementation of the Non-Redundant Error-Correcting Scheme Based on Chaotic Dynamics

This paper presents the design procedure and implementation results of a nonredundant error correcting scheme based on chaotic dynamics using Altera Cyclone III family FPGA board. The scheme is first designed using MATLAB-Simulink then converted to VHDL codes for implementation purposes using the modern tool “Simulink HDL Coder”. The simulation waveforms have been obtained using ModelSim Altera 6.5b.Synthesis reports and board programming files have been obtained using the QUARTUS II 9.1 package. ALTERA-Cyclone III FPGA board has been used as target devices for implementation purpose. The hardware test results show that the coding scheme functions successfully. [Abdullah HN. and Mahmood SK. FPGA Implementation of the No-Redundant Error-Correcting Scheme Based on Chaotic Dynamics. J Am Sci 2014;10(11):25-30]. (ISSN: 1545-1003). http://www.jofamericanscience.org. 4